Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs), programmable input/output blocks (IOBs), and like type programmable elements. The CLBs and IOBs are interconnected by a programmable interconnect structure. An FPGA may also include various dedicated logic circuits, such as memories, digital clock managers (DCMs), and input/output (I/O) transceivers. Notably, an FPGA may include one or more embedded processors. The programmable resource such as, e.g., programmable logic of an FPGA (e.g., CLBs, IOBs, and interconnect structure) is typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells. The bitstream is typically stored in an external nonvolatile memory, such as an erasable programmable read only memory (EPROM). The states of the configuration memory cells define how the CLBs, IOBs, interconnect structure, and other programmable logic are configured. The configuration memory cells typically comprise static random access memory (SRAM) or like type volatile memory cells.
When power is removed from the FPGA, the configuration data is lost. Consequently, when the FPGA again receives power, the configuration data must be reloaded from the nonvolatile source. Use of such an external nonvolatile memory, however, increases the cost of using the FPGA. Furthermore, the large quantity of configuration data that must be loaded in present FPGAs, combined with the limited bandwidth normally afforded the configuration process, leads to a significant delay between when a device is powered and when the device becomes operational. Accordingly, there exists a need in the art for a method and apparatus for initializing a programmable logic device that reduces or eliminates the requirements of an external nonvolatile memory for configuration.